NXP Semiconductors /MIMXRT1064 /FLEXSPI /FLSHCR4

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as FLSHCR4

WMENA=WMENA_0, WMENB=WMENB_0, WMOPT1=WMOPT1_0

Description

Flash Control Register 4

Fields

WMOPT1	Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. 0 (WMOPT1_0): DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode. 1 (WMOPT1_1): DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode.
WMENA	Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set. 0 (WMENA_0): Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. 1 (WMENA_1): Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
WMENB	Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set. 0 (WMENB_0): Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. 1 (WMENB_1): Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.

Links

() ()